1. Field of the Invention
The present invention relates to a phase locking apparatus, a phase locking method, a data reproducing apparatus, a data reproducing method, and programs. More particularly, the invention relates to a phase locking apparatus, a phase locking method, a data reproducing apparatus, a data reproducing method, and programs for stabilizing the performance of the data reproducing apparatus containing the phase locking apparatus regardless of various settings made on the data reproducing apparatus.
2. Description of Related Art
Digital PLL (phase locked loop) apparatus, one of the phase locking apparatuses introduced in recent years, is capable of feedback control based on phase error. This type of control is such that synchronous sampling data, converted from asynchronous sampling data corresponding to RLL code, is output with its waves shaped in equalized relation to a predetermined partial response method. Digital PLL setups are discussed illustratively in Japanese Patent Laid-open No. 2001-358782, Japanese Patent No. 3071142, Japanese Patent Laid-open No. Hei 10-69727, JP-A-H10-508135, Japanese Patent Laid-open No. 2000-76805, Japanese Patent Laid-open No. 2002-42428, and “Interpolated Timing Recovery For Hard Disk Drive Read Channels” by Mark Spurbeck and Richard T. Behrens (Cirrus Logic 1997 IEEE, pp. 1618-1624).